TOS Silver 2000/TOS Silver 2000.iso/Falcon/CENTEK/CENTEK.DOC/040/040CLOCK.TXT

Text File | 1998-07-04 | 5.4 KB | 114 lines

THE MC68040 AND MC68040V CLOCKS

Some people and some companies, especially french ones, announce
the 68040 to be cadenced at 64 MHz on the AFTERBURNER 040 or on
the HADES 040.
This is totally wrong and only reflects the technical ignorance
about the 68040!

The 040 is cadenced by two clocks: the BCLK and the PCLK.
The BCLK (Bus CLocK) cadences the processor, its bus controller, as
well as the entire calculation unit (and the floating unit for
the 'full'  040, meaning with a FPU).
The Motorola DATA BOOK for the 040 is very clear about it because
on page 10-4, we can read: 'All timings are related to BCLK cycles...'
By all means, when you read the instruction timing tables for the
040, and for example, it says that the XXXX instruction is 4 cycles
that means that this instruction is executed in 4 clock BCLK cycles!!
About the PCLK (Processor CLocK), the 040 needs it to cadence its
internal logic, especially its pipeline.
This clock could be 200 or 500 MHz, which wouldn't change the
performance of the 040 !!
In this case, the PCLK is twice the BCLK with a phase shift + or -
250 to 500 ps depending on the clock generator used.
With regards to the design, you can give a PCLK divided by 2 to get
the BCLK.
A more popular approach is the opposite starting with a BCLK multiplied
by 2 with a circuit to obtain the PCLK.
Motorola proposes a MC88915 circuit, which is also used
by the Afterburner.

A remark : the 040 3.3V model only exists in two versions :
- The 68040V which doesn't have an FPU !
- The 68EC040V which has neither an FPU, nor a PMMU !

These two versions are identical to the 5V version regarding the
performance (otherwise, where are the instruction timing tables of
this 3.3V version in the DATABOOK which talks about ALL 040 models ?!!).
The only differences are the 'LOW POWER' possibilities of this 3.3v
version which are explained in the appendix C of the 040 DATA
BOOK. With the version V (like on the 060 !!), there's only one clock
injected in the processor : CLK (CLocK).
Of course, this clock is equal to the BCLK, located at the same
place on the casing as the BCLK !
So why only one clock and what happened to the PCLK ?
You have to know that the 'STATIC' technology allows this 040 (and the 060)
to be cadenced with lower frequencies, even 0 MHz (no clock at all) in
the purpose to reduce consummation as much as possible...
But, the way to exit this mode is to send a non-masked interrupt to the 040.

Therefore, the 040 (and the 060) has an internal clock control logic which
itself is also cadenced by an internal clock, which works constantly !
Yes, it's this logic which gets the interrupt and exits the 040 from its
'low power mode'. This is also the logic which stops or starts the
PLL (phase-lock loop), which has to synchronize the external clock with
the internal clock ! It constantly monitors this PLL and if unphased,
returns an external signal LOC/ (Loss Of Clock).
This signal, for example, is a variation of the CLK sent to the processor.
The clock can only be modified during RESET or LOW POWER MODE !
In the case of an active LOC, it is necessary to send a RESET to
the processor, restarting it again in NORMAL mode.
Therefore, the 040, as well as the 060 can't (in real time) do an
external DX2 like it was possible on some accelerator cards (CENTurbo I
20/40 (1st generation), Speed Resolution Card, HI-Speed 40, 50, etc...).

Let's turn theory into practice:
Just a little demonstration with a FALCON, an Afterburner 040, and
GEMBENCH 4.03 with the INTEGER DIV test which consists of DIVU.W dx,dx.
We read the timings for this DIVU in the Motorola DATABOOK of the 030
and the  040.
For the 030: 44 clock cycles.
For the 040: 27 clock cycles.
We launch GEMBENCH 4.03 and the INTEGER DIV test (ref. FALCON) on:
FALCON STANDARD 16 MHz: 100 % (normal !).
FALCON + AB40 at 32 MHz: 320 % (411 % at 40 MHz).

Here is the equation, no comment.
68040 at 32 MHz = (44/27) x (32/16) = 3.26 or 326 %

On the one hand, we have the theory with the DATABOOK (if some people want
to interpret the DATABOOK differently, we ARE LISTENING!) which gives 326
and on the other hand, a real test on a machine which gives 320 !
So, the hypothesis for the 040 at 32 MHz is proven correct.
If the 040 was at 64 MHz, like some people would like us to believe,
the gembench test should have been closer to:

652 = (44/27) x (64/16) !

A little bit of COMMON SENSE : why would a processor manufacturer
announce on its processors a clock which would only be half of what the
processor calculates for real ?!! Have you ever seen, a manufacturer
half under-estimating its products against the competition?
Moreover, to not even talk about it in its documentations ??!!!
Us, Never !

CONCLUSION : the 68040 is cadenced by the BCLK !

Rodolphe Czuba
Sacha Hnatiuk
David Godec

My only regret is that I placed confidence in what a person and a
magazine said, so I announced the same crap in the first version
of the PHENIX 040/060 presentation file before discovering the truth
myself (during the PHENIX development).
Unfortunately, a lot of people are still fooled by this falsified
information ! Some even were hoodwinked into buying...

Moral : before believing and/or stupidly repeating the proposals of
others, verify for yourself, or verify it with REAL professionals!

Rodolphe Czuba

At CENTEK, we don't like cheaters!